The present invention is related to a semiconductor package constructed by mounting a semiconductor chip on a substrate, and a stacked layer type semiconductor package with employment of the above-described semiconductor package.
While various types of structures of packages for semiconductor chips have been proposed, since electronic appliances on which packages are mounted are manufactured with high performance, there are some cases that, for instance, stacked layer type packages (will also be referred to as “package-on-package (PoP)”) made by stacking conventional packages with each other are employed.
While stacked layer type packages have such structures constructed in such a manner that plural pieces of packages containing semiconductor chips are stacked on each other, since various types of packages can be combined with each other, these stacked layer type packages can be easily adapted to high-performance electronic appliances manufactured in various specifications.    [Patent publication 1] JP-A-2005-347299
However, among current semiconductor chips, total numbers of connection terminals are increased in connection with high performance of these semiconductor chips, namely, a so-called “multiple pin” of semiconductor chips have been popularized. When packages are constructed which can be adapted to semiconductor chips manufactured with the above-described “multiple pins”, total numbers of connection terminals employed in these packages are increased. As a result, there is such a problem that these packages can be hardly stacked with each other.
For example, when packages manufactured with so-called “multiple pins” are stacked with each other, areas used to electrically connect these packages with each other must be secured. As a result, there is another problem that stacked layer type packages become bulky. Further, since there is such a problem that thickness of the stacked layer type packages are increased, there is a further problem that these stacked layer packages can be hardly made thicker. As previously described, no concrete structural example has been proposed as to such stacked layer type packages capable of being adapted to the “multiple pins” and also capable of being made compact.
Further, in the above-described semiconductor chips having high performance and manufactured with the multiple pins, since heat generation amounts of the semiconductor chips are increased, there are some possibilities that various package failures may occur due to thermal cycles of the semiconductor chips.
For instance, general-purpose semiconductor chips are manufactured by silicon. As a result, there is a large difference in thermal expansion coefficients between the silicon and interposers. The interposers are made of resin materials employed in general-purpose packages.
As a consequence, when heat radiation and heat dissipation of the semiconductor chips are repeatedly performed, there is a risk that wire disconnections of packages occur and the packages are broken due to differences in the thermal expansion coefficients between the semiconductor chips and the interposers. Thus, there is another problem that reliability of these packages is lowered.